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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:29:36 04/09/2010 
-- Design Name: 
-- Module Name:    bus_convert_8_32 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bus_convert_8_32 is
    Port ( data_8 : in  STD_LOGIC_VECTOR (7 downto 0);
           data_32 : out  STD_LOGIC_VECTOR (31 downto 0));
end bus_convert_8_32;

architecture Behavioral of bus_convert_8_32 is

begin
P1: process(data_8)
begin 
data_32(7 downto 0) <= data_8;

end process;


end Behavioral;

